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the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd 44164084, 44164184, 44164364 18m-bit ddrii sram 4-word burst operation document no. m 1 5822ej7v 1 ds00 ( 7 th edit i on) date p ubl i s hed ju l y 2004 ns c p(k) printed in japan data sheet 2001 description the pd44164084 is a 2,097,152-word by 8-bit, the pd44164184 is a 1,048,576-word by 18-bit and the pd44164364 is a 524,288-word by 36-bit synchronous double data rate static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. the pd44164084, pd44164184 and pd44164364 integrates unique synchronous peripheral circuitry and a burst counter. all input registers controlled by an input clock pair (k and /k) are latched on the positive edge of k and /k. these products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. these products are packaged in 165-pin plastic bga. features ? 1.8 0.1 v power supply and hstl i/o ? dll circuitry for wide output data valid window and future frequency scaling ? pipelined double data rate operation ? common data input/output bus ? four-tick burst for reduced address frequency ? two input clocks (k and /k) for precise ddr timing at clock rising edges only ? two output clocks (c and /c) for precise flight time and clock skew matching-clock and data delivered together to receiving device ? internally self-timed write control ? clock-stop capability with s restart ? user programmable impedance output ? fast clock cycle time : 4.0 ns (250 mhz), 5.0 ns (200 mhz), 6.0 ns (167 mhz) ? simple control logic for easy depth expansion ? jtag boundary scan
2 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 ordering information part number cycle clock organization core supply i/o package time frequency (word x bit) voltage interface ns mhz v pd44164084f5-e40-eq1 4.0 250 2 m x 8-bit 1.8 0.1 hstl 165-pin plastic pd44164084f5-e50-eq1 5.0 200 bga (13 x 15) pd44164084f5-e60-eq1 6.0 167 pd44164184f5-e40-eq1 4.0 250 1 m x 18-bit pd44164184f5-e50-eq1 5.0 200 pd44164184f5-e60-eq1 6.0 167 pd44164364f5-e50-eq1 5.0 200 512 k x 36-bit pd44164364f5-e60-eq1 6.0 167
3 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 pin configurations / indicates active low signal. 165-pin plastic bga (13 x 15) (top view) [ pd44164084f5-eq1] 1 2 3 4 5 6 7 8 9 10 11 a /cq v ss a r, /w /nw1 /k nc /ld a v ss cq b nc nc nc a nc k /nw0 a nc nc dq3 c nc nc nc v ss a nc a v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v dd q v ss v ss v ss v dd q nc nc dq2 f nc nc nc v dd q v dd v ss v dd v dd q nc nc nc g nc nc dq5 v dd q v dd v ss v dd v dd q nc nc nc h /dll v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd q nc dq1 nc k nc nc nc v dd q v dd v ss v dd v dd q nc nc nc l nc dq6 nc v dd q v ss v ss v ss v dd q nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss a a a v ss nc nc nc p nc nc dq7 a a c a a nc nc nc r tdo tck a a a /c a a a tms tdi a : address inputs tms : ieee 1149.1 test input dq0 to dq7 : data inputs / outputs tdi : ieee 1149.1 test input /ld : synchronous load tck : ieee 1149.1 clock input r, /w : read write input tdo : ieee 1149.1 test output /nw0, /nw1 : nibble write data select v ref : hstl input reference input k, /k : input clock v dd : power supply c, /c : output clock v dd q : power supply cq, /cq : echo clock v ss : ground zq : output impedance matching nc : no connection /dll : dll disable remark refer to package drawing for the index mark.
4 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 165-pin plastic bga (13 x 15) (top view) [ pd44164184f5-eq1] 1 2 3 4 5 6 7 8 9 10 11 a /cq v ss a r, /w /bw1 /k nc /ld a v ss cq b nc dq9 nc a nc k /bw0 a nc nc dq8 c nc nc nc v ss a a0 a1 v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v dd q v ss v ss v ss v dd q nc nc dq6 f nc dq12 nc v dd q v dd v ss v dd v dd q nc nc dq5 g nc nc dq13 v dd q v dd v ss v dd v dd q nc nc nc h /dll v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc nc v dd q v dd v ss v dd v dd q nc dq4 nc k nc nc dq14 v dd q v dd v ss v dd v dd q nc nc dq3 l nc dq15 nc v dd q v ss v ss v ss v dd q nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss a a a v ss nc nc nc p nc nc dq17 a a c a a nc nc dq0 r tdo tck a a a /c a a a tms tdi a0, a1, a : address inputs tms : ieee 1149.1 test input dq0 to dq17 : data inputs / outputs tdi : ieee 1149.1 test input /ld : synchronous load tck : ieee 1149.1 clock input r, /w : read write input tdo : ieee 1149.1 test output /bw0, /bw1 : byte write data select v ref : hstl input reference input k, /k : input clock v dd : power supply c, /c : output clock v dd q : power supply cq, /cq : echo clock v ss : ground zq : output impedance matching nc : no connection /dll : dll disable remark refer to package drawing for the index mark.
5 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 165-pin plastic bga (13 x 15) (top view) [ pd44164364f5-eq1] 1 2 3 4 5 6 7 8 9 10 11 a /cq v ss nc r, /w /bw2 /k /bw1 /ld a v ss cq b nc dq27 dq18 a /bw3 k /bw0 a nc nc dq8 c nc nc dq28 v ss a a0 a1 v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v dd q v ss v ss v ss v dd q nc dq15 dq6 f nc dq30 dq21 v dd q v dd v ss v dd v dd q nc nc dq5 g nc dq31 dq22 v dd q v dd v ss v dd v dd q nc nc dq14 h /dll v ref v dd q v dd q v dd v ss v dd v dd q v dd q v ref zq j nc nc dq32 v dd q v dd v ss v dd v dd q nc dq13 dq4 k nc nc dq23 v dd q v dd v ss v dd v dd q nc dq12 dq3 l nc dq33 dq24 v dd q v ss v ss v ss v dd q nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss a a a v ss nc nc dq10 p nc nc dq26 a a c a a nc dq9 dq0 r tdo tck a a a /c a a a tms tdi a0, a1, a : address inputs tms : ieee 1149.1 test input dq0 to dq35 : data inputs / outputs tdi : ieee 1149.1 test input /ld : synchronous load tck : ieee 1149.1 clock input r, /w : read write input tdo : ieee 1149.1 test output /bw0 to /bw3 : byte write data select v ref : hstl input reference input k, /k : input clock v dd : power supply c, /c : output clock v dd q : power supply cq, /cq : echo clock v ss : ground zq : output impedance matching nc : no connection /dll : dll disable remark refer to package drawing for the index mark.
6 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 pin identification symbol description a0 a1 a synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of k. balls 3a, 10a, and 2a are reserved for the next higher-order address inputs on future devices. all transactions operate on a burst of four words (two clock periods of bus activity). a0 and a1 are used as the lowest two address bits for burst read and burst write operations permitting a random burst start address on x18 and x36 devices. these inputs are ignored when device is deselected or once burst operation is in progress. dq0 to dqxx synchronous data ios: input data must meet setup and hold times around the rising edges of k and /k. output data is synchronized to the respective c and /c data clocks or to k and /k if c and /c are tied to high. x8 device uses dq0 to dq7. x18 device uses dq0 to dq17. x36 device uses dq0 to dq35. /ld synchronous load: this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read/write direction. all transactions operate on a burst of 4 data (two clock periods of bus activity). r, /w synchronous read/write input: when /ld is low, this input designates the access type (read when r, /w is high, write when r, /w is low) for the loaded address. r, /w must meet the setup and hold times around the rising edge of k. /bwx /nwx synchronous byte writes (nibble writes on x8): when low these inputs cause their respective byte or nibble to be registered and written during write cycles. these signals must meet setup and hold times around the rising edges of k and /k for each of the two rising edges comprising the write cycle. see pin configurations for signal to data relationships. k, /k input clock: this input clock pair registers address and control inputs on the rising edge of k, and registers data on the rising edge of k and the rising edge of /k. /k is ideally 180 degrees out of phase with k. all synchronous inputs must meet setup and hold times around the clock rising edges. c, /c output clock: this clock pair provides a user controlled means of tuning device output data. the rising edge of /c is used as the output timing reference for first and third output data. the rising edge of c is used as the output reference for second and fourth output data. ideally, /c is 180 degrees out of phase with c. c and /c may be tied high to force the use of k and /k as the output reference clocks instead of having to provide c and /c clocks. if tied high, c and /c must remain high and not be toggled during device operation. cq, /cq synchronous echo clock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals run freely and do not stop when q tristates. zq output impedance matching input: this input is used to tune the device outputs to the system data bus impedance. dq and cq output impedance are set to 0.2 x rq, where rq is a resistor from this bump to ground. this pin cannot be connected directly to gnd or left unconnected. also, in this product, there is no function to minimize the output impedance by connecting zq directly to v dd q. /dll dll disable: when low, this input causes the dll to be bypassed for stable low frequency operation. tms tdi ieee 1149.1 test inputs: 1.8v i/o levels. these balls may be left not connected if the jtag function is not used in the circuit. tck ieee 1149.1 clock input: 1.8v i/o levels. this pin must be tied to v ss if the jtag function is not used in the circuit. tdo ieee 1149.1 test output: 1.8v i/o level. v ref hstl input reference voltage: nominally v dd q/2. provides a reference voltage for the input buffers. v dd power supply: 1.8v nominal. see dc characteristics and operating conditions for range. v dd q power supply: isolated output buffer supply. nominally 1.5v. 1.8v is also permissible. see dc characteristics and operating conditions for range. v ss power supply: ground nc no connect: these signals are internally connected and appear in the jtag scan chain as the logic level applied to the ball sites. these signals may be connected to ground to improve package heat dissipation.
7 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 block diagram 2 : 1 mux 0 1 /a0' a0' /a0' a0' 0 1 input register e /k r, /w input register e write address register e k r, /w register e output control logic /c c address register e /ld address a0'' a0''' compare output buffer zq dq output enable register c burst logic d1 d0 q1 q0 a1 a0 clk a0' a1' write register memory array write driver sense amps output register a0' clk k e a0''' r /w
8 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 burst sequence linear burst sequence table [ pd44164184, pd44164364] a1, a0 a1, a0 a1, a0 a1, a0 external address 0, 0 0, 1 1, 0 1, 1 1st internal burst address 0, 1 1, 0 1, 1 0, 0 2nd internal burst address 1, 0 1, 1 0, 0 0, 1 3rd internal burst address 1, 1 0, 0 0, 1 1, 0 truth table operation /ld r, /w clk dq write cycle l l l h data in load address, input write data on two input data d(a1) d(a2) d(a3) d(a4) consecutive k and /k rising edge input clock k(t+1) /k(t+1) k(t+2) /k(t+2) read cycle l h l h data out load address, read data on two output data q(a1) q(a2) q(a3) q(a4) consecutive c and /c rising edge output clock /c(t+1) c(t+2) /c(t+2) c(t+3) nop (no operation) h x l h high-z standby(clock stopped) x x stopped previous state remarks 1. h : high level, l : low level, : don?t care, : rising edge. 2. data inputs are registered at k and /k rising edges. data outputs are delivered at c and /c rising edges except if c and /c are high then data outputs are delivered at k and /k rising edges. 3. all control inputs in the truth table must meet setup/hold times around the rising edge (low to high) of k. all control inputs are registered during the rising edge of k. 4. this device contains circuitry that will ensure the outputs will be in high impedance during power-up. 5. refer to state diagram and timing diagrams for clarification. 6. a1 refers to the address input during a write or read cycle. a2, a3 and a4 refer to the next internal burst address in accordance with the linear burst sequence. 7. it is recommended that k = /k = c = /c when clock is stopped. this is not essential but permits most rapid restart by overcoming transmission line charging symmetrically.
9 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 byte write operation [ pd44164084] operation k /k /nw0 /nw1 write dq0 to dq7 l h ? 0 0 ? l h 0 0 write dq0 to dq3 l h ? 0 1 ? l h 0 1 write dq4 to dq7 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remark h : high level, l : low level, : rising edge. [ pd44164184] operation k /k /bw0 /bw1 write dq0 to dq17 l h ? 0 0 ? l h 0 0 write dq0 to dq8 l h ? 0 1 ? l h 0 1 write dq9 to dq17 l h ? 1 0 ? l h 1 0 write nothing l h ? 1 1 ? l h 1 1 remark h : high level, l : low level, : rising edge. [ pd44164364] operation k /k /bw0 /bw1 /bw2 /bw3 write dq0 to dq35 l h ? 0 0 0 0 ? l h 0 0 0 0 write dq0 to dq8 l h ? 0 1 1 1 ? l h 0 1 1 1 write dq9 to dq17 l h ? 1 0 1 1 ? l h 1 0 1 1 write dq18 to dq26 l h ? 1 1 0 1 ? l h 1 1 0 1 write dq27 to dq35 l h ? 1 1 1 0 ? l h 1 1 1 0 write nothing l h ? 1 1 1 1 ? l h 1 1 1 1 remark h : high level, l : low level, : rising edge.
10 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 bus cycle state diagram read double count = count + 2 write double count = count + 2 power up write nop supply voltage provided load new address count = 0 nop advance address by two advance address by two load, count = 4 read load, count = 4 always count = 2 always count = 2 load nop, count = 4 nop, count = 4 remarks 1. a0 and a1 are internally advanced in accordance with the burst order table. bus cycle is terminated after burst count = 4. 2. state transitions: l = (/ld = low); /l = (/ld = high); r = (/r, w = high); w = (/r, w = low). 3. state machine control timing sequence is controlled by k.
11 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit supply voltage v dd ?0.5 +2.9 v output supply voltage v dd q ?0.5 v dd v input voltage v in ?0.5 v dd + 0.5 (2.9 v max.) v input / output voltage v i/o ?0.5 v dd q + 0.5 (2.9 v max.) v operating ambient temperature t a 0 70 c storage temperature t stg ?55 +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70 c) parameter symbol conditions min. typ. max. unit note supply voltage v dd 1.7 1.9 v output supply voltage v dd q 1.4 v dd v 1 high level input voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v 1, 2 low level input voltage v il (dc) ?0.3 v ref ? 0.1 v 1, 2 clock input voltage v in ?0.3 v dd q + 0.3 v 1, 2 reference voltage v ref 0.68 0.95 v notes 1. during normal operation, v dd q must not exceed v dd . 2. power-up: v ih v dd q + 0.3 v and v dd 1.7 v and v dd q 1.4 v for t 200 ms recommended ac operating conditions (t a = 0 to 70 c) parameter symbol conditions min. typ. max. unit note high level input voltage v ih (ac) v ref + 0.2 ? v 1 low level input voltage v il (ac) ? v ref ? 0.2 v 1 note 1. overshoot: v ih (ac) v dd + 0.7 v for t tkhkh/2 undershoot: v il (ac) ? 0.5 v for t tkhkh/2 control input signals may not have pulse widths less than tkhkl (min.) or operate at cycle rates less than tkhkh (min.).
12 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 dc characteristics (t a = 0 to 70c, v dd = 1.8 0.1 v) parameter symbol test condition min. typ. max. unit note x8, x18 x36 input leakage current i li ?2 ? +2 a i/o leakage current i lo ?2 ? +2 a operating supply current i dd v in v il or v in v ih , ?e40 620 ? ma (read write cycle) i i/o = 0 ma ?e50 540 620 cycle = max. ?e60 470 570 standby supply current i sb1 v in v il or v in v ih , ?e40 320 ? ma (nop) i i/o = 0 ma ?e50 270 cycle = max. ?e60 250 high level output voltage v oh(low) |i oh | 0.1 ma v dd q ? 0.2 ? v dd q v 3, 4 v oh note1 v dd q/2?0.12 ? v dd q/2+0.12 v 3, 4 low level output voltage v ol(low) i ol 0.1 ma v ss ? 0.2 v 3, 4 v ol note2 v dd q/2?0.12 ? v dd q/2+0.12 v 3, 4 notes 1. outputs are impedance-controlled. | i oh | = (v dd q/2)/(rq/5) for values of 175 ? rq 350 ? . 2. outputs are impedance-controlled. i ol = (v dd q/2)/(rq/5) for values of 175 ? rq 350 ? . 3. ac load current is higher than the shown dc values. 4. hstl outputs meet jedec hstl class i and class ii standards. capacitance (t a = 25 c, f = 1mhz) parameter symbol test conditions min. typ. max. unit input capacitance c in v in = 0 v 4 5 pf input / output capacitance c i/o v i/o = 0 v 6 7 pf clock input capacitance c clk v clk = 0 v 5 6 pf remark these parameters are periodically sampled and not 100% tested.
13 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 ac characteristics (t a = 0 to 70 c, v dd = 1.8 0.1 v) ac test conditions input waveform (rise / fall time ? 0.3 ns) 0.75 v 0.75 v test points 1.25 v 0.25 v output waveform v dd q / 2 v dd q / 2 test points output load condition figure 1. external load at test v dd q / 2 0.75 v 50 ? z o = 50 ? 250 ? sram v ref zq
14 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 read and write cycle parameter symbol -e40 -e50 -e60 unit note (250 mhz) (200 mhz) (167 mhz) min. max. min. max. min. max. clock average clock cycle time (k, /k, c, /c) tkhkh 4.0 8.4 5.0 8.4 6.0 8.4 ns 1 clock phase jitter (k, /k, c, /c) tkc var ? 0.2 ? 0.2 ? 0.2 ns 2 clock high time (k, /k, c, /c) tkhkl 1.6 ? 2.0 ? 2.4 ? ns clock low time (k, /k, c, /c) tklkh 1.6 ? 2.0 ? 2.4 ? ns clock to /clock (k /k., c /c.) tkh /kh 1.8 ? 2.2 ? 2.7 ? ns clock to /clock (/k k., /c c.) t /khkh 1.8 ? 2.2 ? 2.7 ? ns clock to data clock 200 to 250 mhz tkhch 0 1.8 ? ? ? ? ns (k c., /k /c.) 167 to 200 mhz 0 2.3 0 2.3 ? ? 133 to 167 mhz 0 2.8 0 2.8 0 2.8 < 133 mhz 0 3.55 0 3.55 0 3.55 dll lock time (k, c) tkc lock 1,024 ? 1,024 ? 1,024 ? cycle 3 k static to dll reset tkc reset 30 ? 30 ? 30 ? ns output times c, /c high to output valid tchqv ? 0.45 ? 0.45 ? 0.5 ns c, /c high to output hold tchqx ?0.45 ? ?0.45 ? ?0.5 ? ns c, /c high to echo clock valid tchcqv ? 0.45 ? 0.45 ? 0.5 ns c, /c high to echo clock hold tchcqx ?0.45 ? ?0.45 ? ?0.5 ? ns cq, /cq high to output valid tcqhqv ? 0.3 ? 0.35 ? 0.4 ns 4 cq, /cq high to output hold tcqhqx ?0.3 ? ?0.35 ? ?0.4 ? ns 4 c high to output high-z tchqz ? 0.45 ? 0.45 ? 0.5 ns c high to output low-z tchqx1 ?0.45 ? ?0.45 ? ?0.5 ? ns setup times address valid to k rising edge tavkh 0.5 ? 0.6 ? 0.7 ? ns 5 synchronous load input (/ld), tivkh 0.5 ? 0.6 ? 0.7 ? ns 5 read write input (r, /w) valid to k rising edge data inputs and write data select tdvkh 0.35 ? 0.4 ? 0.5 ? ns 5 inputs (/bwx, /nwx) valid to k, /k rising edge hold times k rising edge to address hold tkhax 0.5 ? 0.6 ? 0.7 ? ns 5 k rising edge to tkhix 0.5 ? 0.6 ? 0.7 ? ns 5 synchronous load input (/ld), read write input (r, /w) hold k, /k rising edge to data inputs and tkhdx 0.35 ? 0.4 ? 0.5 ? ns 5 write data select inputs (/bwx, /nwx) hold
15 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 notes 1. the device will operate at clock frequencies slower than tkhkh(max.). 2. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. it is recommended that the device is kept inactive during these cycles. 4. echo clock is very tightly controlled to data valid / data hold. by design, there is a 0.1 ns variation from echo clock to data. the data sheet parameters reflect tester guardbands and test setup variations. 5. this is a synchronous device. all addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. remarks 1. this parameter is sampled. 2. test conditions as specified with the output loading as shown in ac test conditions unless otherwise noted. 3. control input signals may not be operated with pulse widths less than tkhkl (min.). 4. if c, /c are tied high, k, /k become the references for c, /c timing parameters. 5. v dd q is 1.5 v dc.
16 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 read and write timing tkhkh tkhax q01 q03 k /ld address dq q02 /k 2 4 6 8 10 12 13 135 7911 r, /w qx2 q04 q12q11 q14q13 d21 d23d22 d24 d32d31 d34d33 q41 tkh/kh t/khkh cq /cq c /c tkhch tchqx1 tchqv tchqv tchqx tchqx tcqhqx tcqhqv tchqz tkhkl tklkh tkhkh tkh/kh tdvkh tkhdx tdvkh tkhdx nop read (burst of 4) read (burst of 4) nop nop write (burst of 4) write (burst of 4) read (burst of 4) tkhkl tklkh tkhix tklkh tchcqv tchcqv tchcqx tchcqx a0 a1 a2 a4a3 t/khkh tivkh tavkh tkhch remarks 1. q01 refers to output from address a0. q02 refers to output from the next internal burst address following a0, etc. 2. outputs are disable (high impedance) one clock cycle after a nop. 3. the second nop cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention.
17 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 jtag specification these products support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name pin assignments description tck 2r test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms 10r test mode select. this is the command input for the tap controller state machine. tdi 11r test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo 1r test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. remark the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on the sram power-up. jtag dc characteristics (t a = 0 to 70c, v dd = 1.8 0.1 v, unless otherwise noted) parameter symbol conditions min. typ. max. unit note jtag input leakage current i li 0 v v in v dd ?5.0 ? +5.0 a jtag i/o leakage current i lo 0 v v in v dd q, ?5.0 ? +5.0 a outputs disabled jtag input high voltage v ih 1.3 ? v dd + 0.3 v jtag input low voltage v il ?0.3 ? +0.5 v jtag output high voltage v oh1 | i ohc | = 100 a 1.6 ? ? v v oh2 | i oht | = 2 ma 1.4 ? ? v jtag output low voltage v ol1 i olc = 100 a ? ? 0.2 v v ol2 i olt = 2 ma ? ? 0.4 v
18 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 jtag ac test conditions input waveform (rise / fall time ? 1 ns) 0.9 v 0.9 v test points 1.8 v 0 v output waveform 0.9 v 0.9 v test points output load figure 2. external load at test tdo z o = 50 ? v tt = 0.9 v 20 pf 50 ?
19 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 jtag ac characteristics (t a = 0 to 70 c) parameter symbol conditions min. typ. max. unit note clock clock cycle time t thth 100 ? ? ns clock frequency f tf ? ? 10 mhz clock high time t thtl 40 ? ? ns clock low time t tlth 40 ? ? ns output time tck low to tdo unknown t tlox 0 ? ? ns tck low to tdo valid t tlov ? ? 20 ns tdi valid to tck high t dvth 10 ? ? ns tck high to tdi invalid t thdx 10 ? ? ns setup time tms setup time t mvth 10 ? ? ns capture setup time t cs 10 ? ? ns hold time tms hold time t thmx 10 ? ? ns capture hold time t ch 10 ? ? ns jtag timing diagram t thth t tlov t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo t tlox
20 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 scan register definition (1) register name description instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run-test/idle or the various data register state. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bit?s position in the boundary register. the second column is the name of the input or i/o at the bump and the third column is the bump number. scan register definition (2) register name bit size unit instruction register 3 bit bypass register 1 bit id register 32 bit boundary register 107 bit id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit pd44164084 2m x 8 xxxx 0000 0000 0001 0101 00000010000 1 pd44164184 1m x 18 xxxx 0000 0000 0001 0110 00000010000 1 pd44164364 512k x 36 xxxx 0000 0000 0001 0111 00000010000 1
21 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 scan exit order bit signal name bump bit signal name bump bit signal name bump no. x8 x18 x36 id no. x8 x18 x36 id no. x8 x18 x36 id 1 /c 6r 37 nc nc nc 10d 73 nc nc nc 2c 2 c 6p 38 nc nc nc 9e 74 dq4 dq11 dq20 3e 3 a 6n 39 nc dq7 dq17 10c 75 nc nc dq29 2d 4 a 7p 40 nc nc dq16 11d 76 nc nc nc 2e 5 a 7n 41 nc nc nc 9c 77 nc nc nc 1e 6 a 7r 42 nc nc nc 9d 78 nc dq12 dq30 2f 7 a 8r 43 dq3 dq8 dq8 11b 79 nc nc dq21 3f 8 a 8p 44 nc nc dq7 11c 80 nc nc nc 1g 9 a 9r 45 nc nc nc 9b 81 nc nc nc 1f 10 nc dq0 dq0 11p 46 nc nc nc 10b 82 dq5 dq13 dq22 3g 11 nc nc dq9 10p 47 cq 11a 83 nc nc dq31 2g 12 nc nc nc 10n 48 ? internal 84 nc nc nc 1j 13 nc nc nc 9p 49 a 9a 85 nc nc nc 2j 14 nc dq1 dq11 10m 50 a 8b 86 nc dq14 dq23 3k 15 nc nc dq10 11n 51 a a1 a1 7c 87 nc nc dq32 3j 16 nc nc nc 9m 52 nc a0 a0 6c 88 nc nc nc 2k 17 nc nc nc 9n 53 /ld 8a 89 nc nc nc 1k 18 dq0 dq2 dq2 11l 54 nc nc /bw1 7a 90 dq6 dq15 dq33 2l 19 nc nc dq1 11m 55 /nw0 /bw0 /bw0 7b 91 nc nc dq24 3l 20 nc nc nc 9l 56 k 6b 92 nc nc nc 1m 21 nc nc nc 10l 57 /k 6a 93 nc nc nc 1l 22 nc dq3 dq3 11k 58 nc nc /bw3 5b 94 nc dq16 dq25 3n 23 nc nc dq12 10k 59 /nw1 /bw1 /bw2 5a 95 nc nc dq34 3m 24 nc nc nc 9j 60 r, /w 4a 96 nc nc nc 1n 25 nc nc nc 9k 61 a 5c 97 nc nc nc 2m 26 dq1 dq4 dq13 10j 62 a 4b 98 dq7 dq17 dq26 3p 27 nc nc dq4 11j 63 a a nc 3a 99 nc nc dq35 2n 28 zq 11h 64 /dll 1h 100 nc nc nc 2p 29 nc nc nc 10g 65 /cq 1a 101 nc nc nc 1p 30 nc nc nc 9g 66 nc dq9 dq27 2b 102 a 3r 31 nc dq5 dq5 11f 67 nc nc dq18 3b 103 a 4r 32 nc nc dq14 11g 68 nc nc nc 1c 104 a 4p 33 nc nc nc 9f 69 nc nc nc 1b 105 a 5p 34 nc nc nc 10f 70 nc dq10 dq19 3d 106 a 5n 35 dq2 dq6 dq6 11e 71 nc nc dq28 3c 107 a 5r 36 nc nc dq15 10e 72 nc nc nc 1d
22 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 jtag instructions instructions description extest the extest instruction allows circuitry external to the component package to be tested. boundary- scan register cells at output pins are used to apply test vectors, while those at input pins capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update-ir state of extest, the output driver is turned on and the preload data is driven onto the output pins. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample / preload sample / preload is a standard 1149.1 mandatory public instruction. when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and dq pins into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. sample-z if the sample-z instruction is loaded in the instruction register, all ram dq pins are forced to an inactive drive state (high impedance) and the boundary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction coding ir2 ir1 ir0 instruction note 0 0 0 extest 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 reserved 1 0 0 sample / preload 1 0 1 reserved 1 1 0 reserved 1 1 1 bypass note 1. tristate all dq pins and capture the pad values into a serial scan latch.
23 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 tap controller state diagram test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11 disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k ? resistor. tdo should be left unconnected.
24 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 test logic operation (instruction scan) tck cont roller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive
25 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 test logic (data scan) controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instructi o n register state idcode run-test/idle select-dr-scan select-ir-scan output inactive tck
26 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 package drawing 165-pin plastic bga (13x15) item dimensions d e w e a a1 a2 13.00 0.10 15.00 0.10 0.15 0.40 0.05 1.00 1.40 0.11 1.00 0.50 0.05 (unit:mm) 0.08 0.10 0.20 1.50 0.50 p165f5-100-eq1 x y y1 zd ze b a 11 10 9 8 7 6 5 4 3 2 1 index mark ze zd b s wb e s wa d s y s a a2 a1 e y1 s sx ba b m ? rpmml k jhgfedcba
27 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 recommended soldering condition please consult with our sales offices for soldering conditions of these products. types of surface mount devices pd44164084f5-eq1: 165-pin plastic bga (13 x 15) pd44164184f5-eq1: 165-pin plastic bga (13 x 15) pd44164364f5-eq1: 165-pin plastic bga (13 x 15)
28 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 revision history edition/ page type of location description date this previous revision (previous edition this edition) edition edition 7th edition/ throughout throughout deletion ordering information pd44164364f5-e40-eq1 feb. 2004 p.12 p.12 modification dc characteristics i dd (max.) max. unit max. unit x8, x18 x36 x8, x18 x36 -e40 560 tbd ma -e40 620 ? ma -e50 480 530 -e50 540 620 -e60 410 480 -e60 470 570 dc characteristics i sb1 (max.) max. unit max. unit x8, x18 x36 x8, x18 x36 -e40 250 ma -e40 320 ? ma -e50 210 -e50 270 -e60 190 -e60 250 p.26 p.26 modification package drawing preliminary version standardized version
29 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 [memo]
30 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 [memo]
31 data s heet m158 2 2ej7v 1 ds pd44164084, 44164184, 44164364 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices
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